Simultaneous Multithreaded DSPs: Scaling from High Performance to Low Power

In the DSP world, many media workloads have to perform a specific amount of work in a specific period of time. This observation led us to examine how we can exploit Simultaneous Multithreading for VLIW DSP architectures to: 1) increase throughput in situations where performance is the most important attribute (e.g., base station workloads) and 2) decrease power consumption in situations where performance is bounded by the nature of the workload (e.g., wireless handset workloads). In this paper we discuss how we can multithread a commercial DSP architecture. We study its performance and power characteristics using simulation, compiled code, and realistic workloads that respect real-time constraints. Our results show that a multithreaded DSP (with no additional function units over the base architecture) can easily support a small number of compiled threads without seriously degrading their individual performance. Furthermore, in situations where the required performance is bounded, we show that a multithreaded DSP can perform as well as a non-multithreaded DSP but operating at a reduced clock frequency and low supply voltage (Vdd) with substantial power savings.